by TSMCTW
TSMC's 1.6nm-class process, the first to use backside power delivery. Uses gate-all-around nanosheet transistors.
Volume production ramping in Q4 2026. First Angstrom-class node with backside power delivery.
Updated Apr 2024Checked 10 Oct0 updates this week
Power wiring moves to the back of the chip, freeing the front for signal wiring.
Current flows through thin silicon sheets stacked horizontally. The gate wraps all four sides for better control and lower leakage than fin-shaped transistors.
A16 is designed for AI accelerators and high-performance computing chips that benefit most from the power-delivery and density improvements.
| Spec | A16 process | N2 | Change |
|---|---|---|---|
| Node class | 1.6 nmR (reported) | — | —no comparable change |
| Transistor type | Nanosheet gate-all-aroundR (reported) | N2 nanosheet | —no comparable change |
| Performance gain vs N2 | +8-10%R (reported) | — | —no comparable change |
| Power reduction vs N2 | -15-20%R (reported) | — | —no comparable change |
| Density improvement | +20-23%R (reported) | — | —no comparable change |
| Backside power rail | Super Power RailR (reported) | — | —no comparable change |
R reported by the company
| Spec | A16 process | TSMC A14 process |
|---|---|---|
| Node class | 1.6 nmR (reported) | 1.4 nmR (reported) |
| Transistor type | Nanosheet gate-all-aroundR (reported) | 2nd gen gate-all-around nanosheetR (reported) |
R reported by the company
TSMC
Chip foundry, N2, A16, CoWoS packaging
TSMC, founded in Taiwan in 1987, builds chips that other companies design. It makes most of the world's most advanced chips, including Apple's, NVIDIA's and AMD's. Its CoWoS packaging is a key bottleneck for AI chips.
