by TSMCTW
TSMC's 1.4nm-class process, announced for production in 2028, using second-generation gate-all-around nanosheet transistors. A backside-power version is planned for 2029.
Risk production planned for 2027, volume production for 2028. Backside power version in 2029.
Updated Apr 2025Checked 10 Oct0 updates this week
Improved nanosheet materials and gate dielectrics deliver better performance and lower power. Gate wraps all four sides of the channel.
Designers can mix differently sized cells in one chip to trade off speed and power where it matters most.
The 2028 version uses traditional front-side power. A 2029 version will add backside power delivery like A16.
| Spec | A14 process | A16 | Change |
|---|---|---|---|
| Node class | 1.4 nmR (reported) | — | —no comparable change |
| Transistor type | 2nd gen gate-all-around nanosheetR (reported) | A16 nanosheet | —no comparable change |
| Performance gain vs N2 at same power | +15%R (reported) | — | —no comparable change |
| Power reduction vs N2 at same speed | -30%R (reported) | — | —no comparable change |
| Transistor density improvement vs N2 | +20%R (reported) | — | —no comparable change |
R reported by the company
| Spec | A14 process | TSMC A16 process |
|---|---|---|
| Node class | 1.4 nmR (reported) | 1.6 nmR (reported) |
| Transistor type | 2nd gen gate-all-around nanosheetR (reported) | Nanosheet gate-all-aroundR (reported) |
R reported by the company
TSMC
Chip foundry, N2, A16, CoWoS packaging
TSMC, founded in Taiwan in 1987, builds chips that other companies design. It makes most of the world's most advanced chips, including Apple's, NVIDIA's and AMD's. Its CoWoS packaging is a key bottleneck for AI chips.
