by TSMCTW
TSMC's 3D packaging that stacks logic and memory chips with hybrid bonding. Copper-to-copper connections replace solder bumps.
Scaling with hybrid bonding at 6 micron pitch. AMD uses it for 3D V-Cache.
Checked 10 Oct0 updates this week
Aligned copper pads on adjacent chips are bonded directly in a controlled process, replacing solder bumps with a metal connection.
Different chiplets (logic, memory, I/O) can be made on different nodes and stacked together, mixing old and new processes in one package.
Multiple chiplets stack vertically, moving data through dozens of short vertical connections instead of long horizontal paths.
| Spec | SoIC (System on Integrated Chips) |
|---|---|
| Hybrid bonding pitch (current) | 6 micronsR (reported) |
| Roadmap pitch by 2027 | 4.5 micronsR (reported) |
| Interconnect density vs solder bumping | 56x higherR (reported) |
| Bandwidth improvement | 5x better energy efficiency vs 2015 CoWoSR (reported) |
R reported by the company
TSMC
Chip foundry, N2, A16, CoWoS packaging
TSMC, founded in Taiwan in 1987, builds chips that other companies design. It makes most of the world's most advanced chips, including Apple's, NVIDIA's and AMD's. Its CoWoS packaging is a key bottleneck for AI chips.
