EPYC Venice by AMD: status and timeline

Milestones

Next · Production ramp at TSMC Taiwan facility

EPYC Turin launched2024Complete.
Venice tape-out on TSMC N2Q2 2025Complete.
First wafers and validation completeQ3 2025Complete.
Production ramp at TSMC Taiwan facilityTarget Q2 2026Current milestone.
Commercial launchTarget 2026Not yet reached.

Most important updates

AMD completes tape-out and validation of EPYC Venice on TSMC 2nm process15 Apr 2025

Upcoming

2026Commercial launch (next)
20262026 data-center refresh cycle
Q2 2026Production ramp at TSMC Taiwan facility

Current obstacles

Yield ramp on 2nmNew process nodes start with lower yields; defects and variability must be reduced over months to reach cost-effective production.
Socket and platform compatibilityEPYC sockets and server platforms must be redesigned to support higher power and cooler requirements of 256-core parts.

Physics limits

Single-socket scalability wallA single socket can pack only so many cores before memory bandwidth and latency to reach each core becomes a limiting bottleneck; dual-socket systems require coherent interconnect overhead.
Heat density256 cores at 5 GHz on a 300 mm² die produce 600+ watts in a few square centimetres; removing that heat requires exotic packaging and direct-contact cooling.

How it works

3 parts

Cores

Zen 6 microarchitecture

Zen 6 improves instructions-per-cycle and adds support for newer instruction sets, handling AI workloads and general computing more efficiently than Zen 5c.

Density

2nm process density

TSMC's N2 node uses nanosheet transistors instead of FinFET, packing more transistors and improving power efficiency at the same frequency.

Memory

High-bandwidth DDR5

12 DDR5 channels at 6400 MT/s provide high memory bandwidth to feed the large core count, critical for AI training and inference workloads.

Spec sheet

Spec	EPYC Venice
Maximum cores	256^R (reported)
Manufacturing process	TSMC 2nm (N2)^R (reported)
Core architecture	Zen 6^R (reported)
Performance vs Turin	70% compute gain^R (reported)
Memory channels	12× DDR5-6400 (estimated from Turin specs)^E (estimated)

^R reported by the company · ^E our estimate

Update log

1 update

Tue 15 Apr 2025

Major: AMD completes tape-out and validation of EPYC Venice on TSMC 2nm processPressHardware

About AMD

The team behind EPYC Venice

AMD

Instinct GPUs, Helios racks, EPYC CPUs

AMD designs CPUs and GPUs and is NVIDIA's main rival in AI chips. It pioneered building chips from smaller pieces (chiplets). Its Helios rack, backed by a 6 GW OpenAI deal, is its first full-rack AI system.

OpenAI agreed to deploy 6 GW of AMD GPUs (Oct 2025) and got a warrant for up to 160M AMD shares.
Helios racks with 72 GPUs launched in 2026. First OpenAI capacity due online in Q4 2026.
Bought ZT Systems (closed March 2025) to learn how to build whole racks.

amd.com (opens amd.com)Company profile →

Founded: 196957 yrs
Headquarters: United States
Status: Public
Listed: AMD (opens google.com)NASDAQ
Valuation: public
Staff: ~28,000Dec 2024
Works in: ComputingAI accelerators & CPUsAI
Coverage: 4 programs · 12 updateslatest 23 Jul 2026checked 25 Sep
Customers: OpenAIOracleMeta
Partners: Sanmina (opens sanmina.com)
Suppliers: TSMC
People: Lisa Su (opens en.wikipedia.org)Chair and CEOMark Papermaster (opens en.wikipedia.org)CTO

Spec

EPYC Venice

Maximum cores

256^R (reported)

Manufacturing process

TSMC 2nm (N2)^R (reported)

Core architecture

Zen 6^R (reported)

Performance vs Turin

70% compute gain^R (reported)

Memory channels

12× DDR5-6400 (estimated from Turin specs)^E (estimated)