StoryHardware
AMD completes tape-out and validation of EPYC Venice on TSMC 2nm process
AMD completed tape-out and first-silicon validation of its 6th-generation EPYC Venice processors on TSMC's 2nm N2 process, making Venice the first HPC product to reach this production milestone. The design was validated and production ramp is proceeding on schedule for 2026 launch. AMD also completed bring-up of 5th-generation EPYC processors at TSMC's Arizona Fab 21.
- Venice is the first HPC processor with tape-out on TSMC N2 node
- Zen 6 architecture supports up to 256 cores with 70% compute performance improvement over Turin
- Production ramp scheduled for 2026 commercial launch
- Dual manufacturing strategy includes both Taiwan and future Arizona facility production