HBM4E by SK hynix: status and timeline

HBM4E

Next-generation memory for AI accelerators. 16 Gbps per pin, 48 GB in 12-layer stacks. Delivers 20% better power efficiency than HBM4.

PilotStage 3 of 5

12-layer HBM4E with 16 Gbps per pin shipped to customers in June 2026. Custom-logic variants planned for 2027.

Updated 18 Jun 2026Checked 10 Oct0 updates this week

Milestones

Next · Volume shipments of HBM4E begin

HBM4 mass production rampingJan 2026Complete.
HBM4E development and optimizationQ2 2026Complete.
HBM4E samples ship to customers18 Jun 2026Complete.
Volume shipments of HBM4E beginTarget Jan 2027Not yet reached.

Most important updates

Upcoming

Jan 2027Volume shipments of HBM4E beginin about 12 weeks (next)

Current obstacles

Customer qualificationSamples shipped in June 2026 are in customer evaluation; full qualifications will take months before volume production ramps in 2027.
DRAM refresh constraintsDRAM cells lose charge in milliseconds and require constant refresh, consuming power even at idle. Higher density makes this more pronounced.

Physics limits

Stacking heightHBM4E stacks are height-limited by mechanical and thermal constraints. Growing beyond 12–16 layers requires thinner dies, which worsen heat dissipation.
LatencyTaller stacks increase distance for data movement within the stack, raising access latency. Architecture must balance density against responsiveness.

How it works

3 parts

Dense stacking

12-layer DRAM configuration

SK hynix 10nm-class DRAM enables taller stacks. At 12 layers, HBM4E reaches 48 GB—the same capacity HBM4 needed 16 layers for.

Packaging

Advanced MR-MUF technology

Molded Underfill material between dies improves stability and thermal performance by 17% versus HBM4, reducing heat resistance.

Speed and efficiency

16 Gbps per pin

HBM4E operates at 16 Gbps—37% faster than HBM4—delivering 4 TB/s bandwidth while consuming 20% less power.

Spec sheet

Spec	HBM4E
Stack configuration	12-layer DRAM stacks^R (reported)
Capacity per stack	48 GB^R (reported)
DRAM process	SK hynix 10nm-class 6th-generation (1c DRAM)^R (reported)
Data rate per pin	16 Gbps^R (reported)
Memory bandwidth per stack	4 TB/s^R (reported)
Power efficiency vs HBM4	Over 20% better^R (reported)
Thermal performance vs HBM4	17% better heat dissipation^R (reported)

^R reported by the company

Update log

2 updates

Thu 18 Jun

Major: SK hynix ships 12-layer HBM4E samples to AI customers with 16 Gbps per pinPressHardware

Fri 20 Mar

Minor: SK hynix plans TSMC 3nm for future custom HBM4E logic diesPressManufacturing

About SK hynix

The team behind HBM4E

SK hynix

HBM memory, DRAM, NAND

SK hynix is a South Korean memory chip maker and the leading supplier of high-bandwidth memory (HBM), the stacked memory placed next to AI chips. It is NVIDIA's main HBM supplier.

First to supply HBM3E to customers (March 2024) and first to mass-produce 12-layer HBM3E (Sept 2024).
Completed HBM4 development and readied mass production in September 2025.
Main HBM supplier for NVIDIA's AI GPUs.

skhynix.com (opens skhynix.com)Company profile →

Founded: 198343 yrs
Headquarters: South Korea
Status: Publicof SK Group
Listed: 000660 (opens google.com)KRX
Valuation: public
Works in: ComputingPackaging & memory
Coverage: 2 programs · 8 updateslatest 18 Jun 2026checked 25 Sep
Customers: NVIDIA
Partners: TSMC

Spec

HBM4E

Stack configuration

12-layer DRAM stacks^R (reported)

Capacity per stack

48 GB^R (reported)

DRAM process

SK hynix 10nm-class 6th-generation (1c DRAM)^R (reported)

Data rate per pin

16 Gbps^R (reported)

Memory bandwidth per stack

4 TB/s^R (reported)

Power efficiency vs HBM4

Over 20% better^R (reported)

Thermal performance vs HBM4

17% better heat dissipation^R (reported)