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HBM4SK hynix—HBM4SK hynix—HBM4SK hynix—

HBM4

by SK hynixKR

DeployStage 4 of 5

Development done in September 2025. Ramping for NVIDIA's Rubin GPUs in 2026.

Updated 10 Mar 2026Checked 25 Sep0 updates this week

Milestones

Next · HBM4 volume supply for NVIDIA Rubin
  1. HBM3E 8-layer first supplied to customersMar 2024Complete.
  2. 12-layer HBM3E mass production25 Sep 2024Complete.
  3. HBM4 development completed, mass production readied11 Sep 2025Complete.
  4. HBM4 volume supply for NVIDIA RubinTarget 2026Current milestone.

Most important updates

  • 10 Mar 2026
  • 28 Jan 2026
  • Jan 2026
  • 11 Sep 2025
  • 19 Mar 2025

Upcoming

  1. 2026HBM4 volume supply for NVIDIA Rubin (next)

Current obstacles

  • Stacking yieldOne bad chip can ruin a whole 12-layer stack, so yields are hard to keep high.

Physics limits

  • DRAM bits leak awayEach bit is a little charge on a tiny capacitor that leaks within milliseconds, so every cell is rewritten about every 32–64 ms. Shrinking the capacitor makes leakage worse, which slows density gains.
  • Stacks are height-capped and trap heatThe HBM standard caps a stack at 775 µm, so 16 dies must be thinned to about 30 µm each. Heat from lower dies must pass up through the stack, and DRAM loses data faster when hot.
  • Bandwidth is wires × speedHBM4 already uses 2,048 data wires per stack. More wires need finer bumps that are harder to bond; faster signalling costs more energy per bit.

How it works

2 parts
AMD's Fiji GPU (2015) with four first-generation SK hynix HBM stacks beside it on a silicon interposer; HBM4 stacks sit the same way
AMD's Fiji GPU (2015) with four first-generation SK hynix HBM stacks beside it on a silicon interposer; HBM4 stacks sit the same wayPhoto: C. Spille/pcgameshardware.de · CC BY-SA 4.0 (opens commons.wikimedia.org)
Stack

Memory chips in a tower

12 thin DRAM chips are stacked and linked by thousands of tiny vertical wires.

Width

Very wide connection

2,048 connections per stack let data flow to the AI chip much faster than normal memory.

Spec sheet

vs HBM3E
SpecHBM4HBM3EChange
Interface width2,048 bitsR (reported)1,024 bits▲ 1,024 bits
Data rate per pinOver 10 GbpsR (reported)——no comparable change

R reported by the company

Update log

5 updates

Tue 10 Mar

  • Minor: PressHardware

Wed 28 Jan

  • Minor: PressCommercial

Jan 2026

  • Minor: PressHardware

Thu 11 Sep 2025

  • Major: PressHardware

Wed 19 Mar 2025

  • Major: PressHardware

About SK hynix

The team behind HBM4

SK hynix

HBM memory, DRAM, NAND

SK hynix is a South Korean memory chip maker and the leading supplier of high-bandwidth memory (HBM), the stacked memory placed next to AI chips. It is NVIDIA's main HBM supplier.

  • First to supply HBM3E to customers (March 2024) and first to mass-produce 12-layer HBM3E (Sept 2024).
  • Completed HBM4 development and readied mass production in September 2025.
  • Main HBM supplier for NVIDIA's AI GPUs.

skhynix.com (opens skhynix.com)Company profile →

Founded
198343 yrs
Headquarters
South Korea
Status
Publicof SK Group
Listed
000660 (opens google.com)KRX
Valuation
public
Works in
ComputingPackaging & memory
Coverage
1 program · 6 updateslatest 10 Mar 2026checked 25 Sep
Customers
NVIDIA
Partners
TSMC
Primer