TSMC reportedly widens CoWoS outsourcing to ASE and SPIL, adding the chip-on-wafer step

ASE Technology/Leading-edge advanced packaging (VIPack)

TSMC is reported to be outsourcing the chip-on-wafer step of CoWoS, placing dies on the interposer, to packaging houses including ASE and SPIL. Until now they mostly handled the later substrate step; ASE and SPIL are building their own lines with customer backing including AMD.

• Chip-on-wafer (dies onto interposer) added to the substrate step OSATs already did.
• ASE and SPIL set aside part of 2026 capex for their own CoW lines.
• TSMC CoWoS capacity seen rising from about 70,000 to 130,000–140,000 wafers a month by end-2026.
• A roughly 20% supply gap expected in 2026 despite the expansion.