Leading-edge advanced packaging (VIPack) by ASE Technology: status and timeline

Leading-edge advanced packaging (VIPack)

Become the main second source to TSMC for AI chip packaging, the step that has limited how many AI accelerators can be shipped.

ScalingStage 5 of 5

In volume and growing fast: 2026 spending $10.5B, panel line to mass production in early 2027.

Updated 5 Aug 2026Checked 11 Oct0 updates this week

Milestones

Next · K28 CoWoS and test plant due for completion in Kaohsiung

K27 Kaohsiung plant starts operating2023Complete.
FOCoS-Bridge with eight HBM stacks shown31 May 2023Complete.
FOCoS-Bridge with through-silicon vias28 May 2025Complete.
Automated 310 mm panel-level line unveiled26 May 2026Complete.
K28 CoWoS and test plant due for completion in KaohsiungTarget Q4 2026Current milestone.
Panel-level line enters mass productionTarget Q1 2027Not yet reached.

Most important updates

Upcoming

Q4 2026K28 CoWoS and test plant due for completion in Kaohsiung (next)
Q1 2027Panel-level line enters mass production

Current obstacles

Building capacity fast enoughDemand for AI packaging still outruns supply; ASE is running 13 new plants and 8 expansions, and buying existing factories to move faster.
TSMC keeps the hardest stepsTSMC hands out mainly simpler parts of CoWoS; ASE must prove it can do the full process at the yields AI chip makers demand.

Physics limits

Fine wiring is hard to make on large areasWires a couple of microns wide must be defect-free across a package many times the size of a chip. One flaw can scrap several expensive dies, so yield drops as packages grow.
Different materials warp with heatSilicon, copper and organic substrate expand at different rates when heated. Large packages bend during bonding and use, which can crack joints.
Moving data off-chip costs energyEven short package wires take far more energy per bit than wires inside a chip, so packaging limits how efficiently multi-chip AI systems can scale.

How it works

3 parts

Base

Chips and memory side by side

An AI processor needs stacked HBM memory millimetres away. Both are placed on a base with thousands of fine wires, which then sits on a larger substrate.

Bridges

Silicon only where it is needed

Small silicon bridges under chip edges carry dense links; cheaper fan-out wiring does the rest. Vias through the bridges cut power loss threefold.

Panels

Square panels for big packages

AI packages are now several times a chip's maximum size. Square 310 mm panels fit more of them than round wafers and waste less of the edge.

Spec sheet

Spec	Leading-edge advanced packaging (VIPack)
Leading-edge packaging revenue 2025	$1.6B^R (reported)
2027 revenue target	At least $7.5B^R (reported)
2026 capital spending	$10.5B (record)^R (reported)
Usable area per panel	Up to 96,100 mm²^R (reported)
FOCoS finest wiring (line/space)	2 µm / 2 µm^R (reported)

^R reported by the company

Papers & demos

1 item

31 May 2023demo
FOCoS-Bridge: two ASICs and eight HBM stacks in one 70 x 78 mm fan-out package (opens aseglobal.com)Showed interposer-like chip-to-chip wiring without a reticle-limited silicon interposer.

Update log

5 updates

About ASE Technology

The team behind Leading-edge advanced packaging (VIPack)

ASE Technology

Chip packaging and test (OSAT), CoWoS second source

ASE is the world's largest outsourced chip packaging and testing company, formed from ASE and SPIL. It wires finished chips into packages, and increasingly builds the advanced multi-chip packages that AI processors need, taking overflow work from TSMC.

2026 capital spending raised twice, to a record $10.5B, mostly for AI packaging and test.
Leading-edge packaging revenue was $1.6B in 2025; the 2027 target is at least $7.5B.
TSMC now outsources parts of its CoWoS process to ASE and SPIL to ease the AI packaging crunch.

Company profile →

Founded: 198442 yrs
Headquarters: Taiwan
Status: Public
Listed: ASX (opens google.com)NYSE
Valuation: public
Works in: ComputingPackaging & memory
Coverage: 1 program · 5 updateslatest 5 Aug 2026checked 11 Oct
Customers: AMD (opens trendforce.com)
Partners: TSMC (opens trendforce.com)NVIDIA (opens trendforce.com)
People: Jason Chang (opens en.wikipedia.org)Co-founder & ChairmanTien Wu (opens taipeitimes.com)Chief Operating OfficerJoseph Tung (opens taipeitimes.com)Chief Financial Officer

Spec

Leading-edge advanced packaging (VIPack)

Leading-edge packaging revenue 2025

$1.6B^R (reported)

2027 revenue target

At least $7.5B^R (reported)

2026 capital spending

$10.5B (record)^R (reported)

Usable area per panel

Up to 96,100 mm²^R (reported)

FOCoS finest wiring (line/space)

2 µm / 2 µm^R (reported)

Leading-edge advanced packaging (VIPack)

Milestones

Most important updates

Upcoming

Current obstacles

Physics limits

How it works

Chips and memory side by side

Silicon only where it is needed

Square panels for big packages

Spec sheet

Papers & demos

Update log

Wed 5 Aug

Thu 30 Jul

Tue 26 May

Feb 2026

Wed 28 May 2025

About ASE Technology

Current obstacles

Physics limits

How it works

Chips and memory side by side

Silicon only where it is needed

Square panels for big packages

Spec sheet

Papers & demos

Update log

Wed 5 Aug

Thu 30 Jul

Tue 26 May

Feb 2026

Wed 28 May 2025

About ASE Technology