Advanced packaging

Techniques for joining several chips so closely in one package that they behave almost like a single chip.

• A package used to be a protective shell with pins; now the wiring between chips inside it is often what limits performance.
• In '2.5D', chips sit side by side on a silicon 'interposer' with wiring far finer than a circuit board; TSMC's CoWoS joins GPUs to HBM this way.
• In '3D', dies are stacked and bonded copper pad to copper pad, with connections only a few micrometres apart.
• CoWoS capacity was a key bottleneck on AI chip supply in 2023–25, which turned packaging plants into strategic investments.