The brief
- Deployed first full-stack silicon CMOS system to UK NQCC (Sept 2025); four-qubit unit cell on 300mm wafers.
- DARPA QBI Stage B selected (Nov 2025); one of 11 advancing from 18; ~$15M funding for one year.
- 100x lower cost, 100x less space, 1,000x less power than cryogenic systems; path to millions of qubits.
Technical approach
Standard foundry process on 300mm wafers
Same process as smartphones and laptops; leverages decades of cost learning.
Electron spins in silicon dots
Single electrons trapped in potential wells; spin rotations via electric/magnetic fields.
Transistor-like scaling to millions of qubits
Thousands of qubits on current wafers; millions as feature sizes shrink.
GlobalFoundries partnership
Access to cutting-edge nodes and volume manufacturing capability.

