HBM3E & DRAM by ChangXin Memory Technologies: status and timeline

Milestones

Next · HBM3E 12-high mass production target

HBM3E 8-high mass production begins2026Complete.
HBM3E 12-high mass production targetTarget Q4 2026Current milestone.
DRAM output reaches 350,000 wafers per monthTarget Q4 2026Not yet reached.
Shanghai IPO (STAR market) listing27 Jul 2026Complete.
HBM3E 40,000 wpm; total DRAM 420,000 wpmTarget Q4 2027Not yet reached.

Most important updates

CXMT plans to mass-produce HBM3E 12-high starting in 2027 after HBM3E 8-high reaches mass production in 2026Apr 2026

Upcoming

Q4 2026HBM3E 12-high mass production target (next)
Q4 2026DRAM output reaches 350,000 wafers per month
Q1 2027New fab starts wafer output
Q4 2027HBM3E 40,000 wpm; total DRAM 420,000 wpm

Current obstacles

Yield on 12-high stacks8-high to 12-high increases defect sensitivity. Yields must hit 70%+ for viability.
Customer qualificationT-Head, Cambricon must qualify CXMT memory. Long cycles risk delaying revenue.
Export controlsU.S. restrictions on advanced memory may interrupt supply chains for equipment.

Physics limits

Fab capacity is fixed by constructionEven with new fabs under construction, CXMT's 2027 output is capped by building timelines. Unexpected construction delays directly delay production targets.
Thermal density in HBMStacking 12 DRAM dies in one package concentrates power dissipation. Beyond 12-high, heat removal becomes the limiting factor without new cooling architectures.
Logic die integrationCXMT's in-house logic die may lag Samsung or SK Hynix in efficiency. Third-party logic integration adds cost and qualification time.

How it works

3 parts

Stacking

Vertical chip stacking

8 or 12 DRAM dies stack vertically using micro-bumps and TSVs, boosting bandwidth density.

Logic Layer

Logic base die

Logic die routes data between stack and interfaces. CXMT integrates its own.

Heat Management

Thermal design

Advanced substrates and thermal interfaces manage heat from stacked dies at AI datacenter power.

Spec sheet

Spec	HBM3E & DRAM
DRAM wafers per month (current)	~320,000^E (estimated)
DRAM target end 2026	350,000^R (reported)
DRAM target end 2027	420,000^R (reported)
HBM wafers per month (end 2026)	10,000^E (estimated)
HBM wafers per month (end 2028)	40,000^R (reported)
HBM3E stacks produced in 2027 (estimate)	3–4 million^E (estimated)

^R reported by the company · ^E our estimate

Update log

1 update

Apr 2026

Major: CXMT plans to mass-produce HBM3E 12-high starting in 2027 after HBM3E 8-high reaches mass production in 2026PressHardware

About ChangXin Memory Technologies

The team behind HBM3E & DRAM

ChangXin Memory Technologies

China DRAM HBM3E memory chips manufacturing

CXMT is China's largest DRAM maker. Founded in 2016 to reduce import reliance, it produces DDR5, LPDDR5X, and HBM3E. Listed on Shanghai's STAR market in July 2026 with an $8.6 billion IPO.

Shifting 20% of DRAM output to HBM3E: 8-high in 2026, 12-high by late 2026, scaling to 40,000 wpm by 2028.
Plans 3–4M HBM3E stacks in 2027 to supply China's AI GPU demand from T-Head, Cambricon.
Total DRAM capacity reaches 350,000 wpm by end 2026, narrowing gap with Samsung, SK Hynix, Micron.

cxmt.com (opens cxmt.com)Company profile →

Founded: 201610 yrs
Headquarters: China
Status: Public
Valuation: $8.6Bdeal valueJul 2026
Works in: ComputingPackaging & memory
Coverage: 1 program · 2 updateslatest 1 Jul 2026checked 11 Oct
Customers: T-Head (Alibaba) (opens alibaba.com)Cambricon (opens cambricon.com)

Spec

HBM3E & DRAM

DRAM wafers per month (current)

~320,000^E (estimated)

DRAM target end 2026

350,000^R (reported)

DRAM target end 2027

420,000^R (reported)

HBM wafers per month (end 2026)

10,000^E (estimated)

HBM wafers per month (end 2028)

40,000^R (reported)

HBM3E stacks produced in 2027 (estimate)

3–4 million^E (estimated)