BiCS FLASH 10 by Kioxia: status and timeline

BiCS FLASH 10

Store more data per chip, read it faster and use less power, so AI data centres can keep huge datasets on flash at lower cost per terabyte.

PilotStage 3 of 5

Sampling since Jul 2026, with first production at Kitakami Fab2; mass production reported for 2027.

Updated 30 Jul 2026Checked 11 Oct0 updates this week

Milestones

Next · Mass production at Kitakami Fab2 (reported target)

Kitakami Fab2 opens, first making 218-layer BiCS 829 Sep 2025Complete.
BiCS FLASH 10 samples ship (1Tb TLC)3 Jul 2026Complete.
10th-gen production begins at Kitakami Fab23 Jul 2026Complete.
CM10 PCIe 6.0 SSDs on BiCS 10 sampling30 Jul 2026Complete.
Mass production at Kitakami Fab2 (reported target)Target 2027Not yet reached.

Most important updates

Upcoming

2027Mass production at Kitakami Fab2 (reported target) (next)

Current obstacles

Ramping a new generationYields on a new 332-layer process start low and improve with volume; output must grow fast while prices are high.
Racing taller rivalsCompetitors stack over 400 layers; Kioxia must win on cost per bit, speed and power with fewer layers.

Physics limits

Deep holes are hard to etchChannel holes through hundreds of layers are dozens of times deeper than wide; keeping them straight and even is ever harder, so stacks are built in tiers.
Fewer electrons per levelSmaller cells and more bits per cell leave only a handful of electrons between levels, so data leaks and wears out faster and needs stronger error correction.
Writes wear cells outEach write pushes electrons through an insulator and slowly damages it, so flash survives a limited number of rewrites, fewer as bits per cell rise.

How it works

4 parts

Cells

Charge stored in a tiny trap

Each cell holds electrons in an insulating layer; how many it holds sets the stored bits. TLC packs 3 bits by using 8 charge levels.

Stack

332 layers in vertical strings

Holes are etched down through hundreds of alternating layers, then lined to form cells stacked like floors of a tower.

CBA

Control logic bonded on top

The circuits that read and write cells are made on a separate wafer and bonded to the memory, giving faster logic and more cell area.

OPS

Tighter packing sideways

A denser layout of the gates at the top of each string squeezes more strings into the same area, adding density without more layers.

Spec sheet

vs BiCS FLASH 8 (218 layers)

Spec	BiCS FLASH 10	BiCS FLASH 8 (218 layers)	Change
Stacked layers	332^R (reported)	218 (BiCS 8)	▲ 114
Chip capacity	1 Tb TLC (3 bits per cell)^R (reported)	—	—no comparable change
NAND interface speed	4.8 Gb/s (+33% vs gen 8)^R (reported)	—	—no comparable change
Bit density vs gen 8	+59%^R (reported)	—	—no comparable change
Read power efficiency vs gen 8	+30%^R (reported)	—	—no comparable change
Write power efficiency vs gen 8	+18%^R (reported)	—	—no comparable change

^R reported by the company

Update log

4 updates

About Kioxia

The team behind BiCS FLASH 10

Kioxia

3D NAND flash, enterprise SSDs

Kioxia makes NAND flash memory, the chips inside SSDs and phones, and its own data-centre SSDs. It is the former Toshiba memory business, which invented NAND in 1987, and builds its flash in Japan in fabs shared with SanDisk.

AI data centres drive a flash boom: on 12 June 2026 Kioxia's market value passed Toyota's, making it Japan's most valuable listed company.
BiCS FLASH 10, with 332 layers, began sampling and production at Kitakami Fab2 in July 2026.
Fabs are run jointly with SanDisk, a partnership extended to December 2034.

kioxia.com (opens kioxia.com)Company profile →

Founded: 20179 yrs
Headquarters: Japan
Status: Public
Valuation: public
Works in: ComputingPackaging & memory
Coverage: 1 program · 5 updateslatest 30 Jul 2026checked 11 Oct
Partners: SanDisk (opens sandisk.com)
Investors: Bain Capital
People: Hiroo Ota (opens kioxia-holdings.com)President and CEOStacy J. Smith (opens kioxia-holdings.com)Executive ChairmanHideshi Miyajima (opens kioxia-holdings.com)Chief Technology Officer

Spec

BiCS FLASH 10

BiCS FLASH 8 (218 layers)

Change

Stacked layers

332^R (reported)

218 (BiCS 8)

▲ 114

Chip capacity

1 Tb TLC (3 bits per cell)^R (reported)

—

—no comparable change

NAND interface speed

4.8 Gb/s (+33% vs gen 8)^R (reported)

—

—no comparable change

Bit density vs gen 8

+59%^R (reported)

—

—no comparable change

Read power efficiency vs gen 8

+30%^R (reported)

—

—no comparable change

Write power efficiency vs gen 8

+18%^R (reported)

—

—no comparable change

BiCS FLASH 10

Milestones

Most important updates

Upcoming

Current obstacles

Physics limits

How it works

Charge stored in a tiny trap

332 layers in vertical strings

Control logic bonded on top

Tighter packing sideways

Spec sheet

Update log

Thu 30 Jul

Fri 3 Jul

Mon 29 Sep 2025

About Kioxia

Current obstacles

Physics limits

How it works

Charge stored in a tiny trap

332 layers in vertical strings

Control logic bonded on top

Tighter packing sideways

Spec sheet

Update log

Thu 30 Jul

Fri 3 Jul

Mon 29 Sep 2025

About Kioxia