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WSE-3 / CS-3Cerebras—Cerebras—
WSE-3 / CS-3
Photo: Steve Jurvetson · CC BY 4.0 (opens flickr.com)

WSE-3 / CS-3

by CerebrasUS

ScalingStage 5 of 5

Shipping in CS-3 systems and running Cerebras's inference cloud.

Updated 14 Jan 2026Checked 25 Sep0 updates this week

Milestones

No announced next step
  1. WSE-1 unveiledAug 2019Complete.
  2. WSE-2 (7 nm, 2.6T transistors)Apr 2021Complete.
  3. WSE-3 (5 nm, 4T transistors)13 Mar 2024Complete.
  4. Cerebras Inference cloud launched27 Aug 2024Complete.

Most important updates

  • 14 Jan 2026
  • Apr 2025
  • Mar 2025
  • 27 Aug 2024
  • 13 Mar 2024

Current obstacles

  • Memory capacity per wafer44 GB of on-chip memory is fast but small, so big models must be split across many wafers.

Physics limits

  • SRAM is fast but not denseOn-chip SRAM needs six transistors per bit and has barely shrunk on recent nodes. Even a whole wafer holds only 44 GB, so large models must be spread over many wafers or streamed in.
  • A wafer is the largest possible chipWafers are 300 mm across, so the biggest square chip is about 46,000 mm². Beyond that, compute grows only by linking wafers, which brings back the slower off-chip links wafer-scale was meant to avoid.
  • Defects are certain at this sizeEvery wafer has defects, so a wafer-sized chip must carry spare cores and route around failures. That redundancy costs area, and some fraction of wafers still has too many faults to use.

How it works

4 parts
A Cerebras wafer-scale cluster: rows of Cerebras systems, each built around a single wafer-sized chip, fed by the cabling overhead
A Cerebras wafer-scale cluster: rows of Cerebras systems, each built around a single wafer-sized chip, fed by the cabling overheadCourtesy of Cerebras Systems · Press kit, editorial use (opens cerebras.ai)
Wafer

One chip per wafer

Instead of cutting a wafer into many chips, the whole 46,225 mm² square is one processor with about 900,000 cores and 4 trillion transistors.

Memory

Memory beside every core

44 GB of SRAM is spread among the cores, giving about 21 PB/s of bandwidth, so weights don't wait on external memory.

Defects

Built-in spares

Spare cores and rerouting let the chip work around the defects that every wafer has.

Scale

Streaming weights for training

For training, weights live in external MemoryX units and stream in layer by layer; SwarmX links many CS-3 systems.

Update log

5 updates

Wed 14 Jan

  • Major: BlogCommercial

Apr 2025

  • Minor: PressPartnership

Mar 2025

  • Minor: PressCommercial

Tue 27 Aug 2024

  • Minor: BlogCommercial

Wed 13 Mar 2024

  • Major: PressHardware

About Cerebras

The team behind WSE-3 / CS-3

Cerebras

Wafer-size AI chips, inference cloud

Cerebras builds an AI chip the size of a whole silicon wafer, and sells systems and a fast AI cloud. It listed on Nasdaq in May 2026 in one of the year's biggest tech IPOs.

  • IPO priced at $185 per share on 14 May 2026, raising about $5.55B.
  • WSE-3 packs 4 trillion transistors and 44 GB of on-chip memory on one wafer.
  • Signed a multi-year inference deal with OpenAI in January 2026.
Founded
201610 yrs
Headquarters
United States
Status
Public
Valuation
public
Raised
$1.1B1 round
Last round
IPO · $5.5BMay 2026
Works in
ComputingAI chipsAI
Coverage
1 program · 7 updateslatest 14 May 2026checked 25 Sep
Lead investors
FidelityAtreides Management
Customers
OpenAIG42
Suppliers
TSMC
People
Andrew FeldmanCo-founder and CEO
Primer