by MatXUS
A custom AI chip optimized for language model training and inference. Targets 2,000+ tokens/second on 100-layer mixture-of-experts using a hybrid SRAM-first architecture for low-latency inference.
Development ongoing. Tapeout targeted within a year of February 2026. Volume production planned for 2027.
Updated 24 Feb 2026Checked 10 Oct0 updates this week
A custom compute fabric designed to maximize throughput on the matrix operations that dominate transformer models.
Weights and computations use SRAM for fast access; long-context caches use HBM stacks placed adjacent to the die.
| Spec | MatX One |
|---|---|
| Target throughput (100-layer MoE) | 2,000+ tokens/secondR (reported) |
R reported by the company
MatX
LLM chips, systolic arrays, custom AI silicon
MatX designs AI chips specifically optimized for large language model training and inference. Founded by ex-Google TPU engineers, it is building the MatX One chip with a hybrid SRAM-first architecture, targeting volume production in 2027.
